1. Field of the Invention
The present invention relates to a package having an Au layer, a semiconductor device having such an Au layer, and a method of mounting the semiconductor device, which can prevent a positional deviation between semiconductor devices and a package substrate even when exposed to a high temperature of 500.degree. C. or above after the mounting of the semiconductor devices on the package substrate.
2. Description of the Related Art
The attachment of a device to the position of a die pad such as a lead frame for a ceramic package and a plastic shielded package is called "die bonding." This die bonding can allow a device to mechanically and electrically connected to a package substrate and can cause heat generated from the device to be easily discharged. In general, die bonding requires that ohmic connection as well as stable mechanical and chemical bonding should be provided at the junction between a package substrate and the back of a device.
Die bonding techniques or methods of mounting semiconductor devices on a package substrate mainly include resin adhesion, an Au--Si eutectic alloy techniques, a soldering technique and an Au--Au eutectic technique. Method of bonding semiconductor components using such die bonding and packages fabricated using such die bonding are disclosed in Unexamined Japanese Patent Publication No. Hei 6-177135 (hereinafter called "first prior art") and Unexamined Japanese Patent Publication No. Hei 7-263788 (hereinafter called "second prior art").
FIG. 1 is a side view showing method of bonding a semiconductor components according to the first prior art. First, a barrier layer 21 of tungsten or the like is selectively formed on the surface of a submount body 20. Next, nickel-tin alloy and tungsten are simultaneously sputtered on the barrier layer 21 to form an auxiliary layer 22. Then, a wet layer 23 of nickel-tin alloy is deposited on the auxiliary layer 22. Then, gold and tin are alternately vapor-deposited on the wet layer 23, thus forming a solder layer 24. It is preferable that the area of this solder layer 24 which is in contact with the wet layer 23 and the top surface of the solder layer 24 should be formed of gold.
A laser element 8 which is to be bonded to the submount body 20 has a laser chip 9 formed of semiconductor in a III-V group, and an ohmic contact layer 10 formed on the surface of the laser chip 9 which is bonded to the submount body 20. A titanium layer 11, a platinum layer 12 and a gold layer 13 are sequentially and selectively deposited on the surface of this ohmic contact layer 10.
In bonding the thus formed submount body 20 and laser element 8 together, the submount body 20 and the laser element 8 are placed with the gold layer 13 in contact with the solder layer 24, and force 15 is applied to both at a temperature of approximately 320 to 340.degree. C.
In this first prior art, the barrier layer 21 is formed of W, Mo, Cr or Ru. This barrier layer 21 serves to prevent the melting temperature of the solder layer 24 to increase. Generally, when silicon is diffused into the solder layer 24 formed of gold and tin, from the substrate, the melting temperature of the solder layer 24 increases. Therefore the barrier layer 21 can prevent the diffusion of silicon into the solder layer 24 from the substrate, thereby preventing the melting temperature of the solder layer 24 from increasing.
FIG. 2 is a perspective view showing a semiconductor laser device according to the second prior art. First, Ni is vapor-deposited on the surface of a heat sink 36 to form a barrier layer 35. Next, a low-melting point solder layer 34 of In, Sn or their alloy is selectively formed on the barrier layer 35. A p-type electrode 33 is formed on one surface of a semiconductor laser element 31 and an n-type electrode 32 is formed on the other surface thereof. The heat sink 36 is then heated to approximately 200.degree. C. to melt the low-melting point solder layer 34, after which the p-type electrode 33 formed on the semiconductor laser element 31 is pressed against the low-melting point solder layer 34. Thereafter, both are cooled down so that the semiconductor laser element 31 is bonded to the heat sink 36.
According to this second prior art, Ni, W and Mo are used for the barrier layer 35. This barrier layer 35 serves to prevent Cu in the heat sink 36 from being diffused into the semiconductor laser element 31. Without the barrier layer 35, Cu would be diffused into the semiconductor laser element 31, deteriorating the laser output.
As the integration of semiconductor devices and the packing density thereof become higher and higher recently, the precision on the order of micrometers is demanded of the mount positions of semiconductor devices on a package substrate and the distances between adjoining semiconductor devices. In the case where a package substrate and semiconductor devices mounted on this package substrate are exposed to a high temperature, as in the case where a field discharge type electron source is used in a CRT (Cathode-Ray Tube), a die bonding technique which is excellent in heat resistance is demanded.
Because the melting temperature of the solder layer 24 is normally less than 400.degree. C. in the first prior art, however, the solder layer 24 is melted if the package is exposed to a temperature of over 400.degree. C. As the barrier layer 21 prevents the melting temperature of the solder layer 24 from becoming higher, melting of the solder layer 24 becomes easier.
Likewise, the solder layer 34 is made of metal whose melting temperature is low, e.g., approximately 200.degree. C., in the second prior art, so that the solder layer 34 is melted if the package is exposed to a temperature of over 400.degree. C.
Further, the barrier layer 35 merely serves to prevent Cu in the heat sink 36 from being diffused into the semiconductor laser element 31, but does not improve the heat resistance of the junction.
According to the first and second prior arts, as apparent from the above, when a package fabricated by mounting semiconductor devices on a package substrate is exposed to a temperature of over, for example, 400.degree. C., the junction is melted, the misalignment of the semiconductor devices to the package substrate is likely to occur. As the junction is less durable to a high temperature, therefore, it is difficult to set the mount positions of the semiconductor devices on the package substrate and the distances between adjoining semiconductor devices at a high accuracy.
The Au--Au eutectic technique is one die bonding technique which gives a high heat resistance to the junction between a package substrate and semiconductor devices and ensures a high precision of alignment of the semiconductor devices to the package substrate. This Au--Au eutectic technique will be discussed below.
According to the Au--Au eutectic technique, an Au film is formed on the back surface of an Si substrate of semiconductor devices and also on the top surface of a package substrate, the Si substrate and the package substrate are arranged with their Au films facing each other, and the semiconductor device and the package substrate are rubbed (scrubbed) against each other while applying a load on both Au films. Consequently, Au--Au eutectic layer is formed so that the semiconductor devices and the package substrate are connected together. There are two scrubbing methods: one is an ultrasonic scrubbing method which applies ultrasonic waves to both Au films so that the semiconductor devices and the package substrate are scrubbed against each other by the ultrasonic vibration, and the other is a pressure scrubbing method which vibrates both Au films while mechanically applying a load on the semiconductor devices and the package substrate.
In either way, because Au as an adhesive has a high melting point of 1064.43.degree. C., once semiconductor devices are connected to a package substrate, no misalignment occurs at the junction even if the package is exposed to a high temperature. With the ultrasonic scrubbing method in use, as the amplitude of ultrasonic waves ranges from -1 .mu.m to +1 .mu.m, misalignment hardly occurs at the time of making the connection. In other words, the Au--Au eutectic technique ensures a high heat resistance and a high precision of alignment at the junction between a package substrate and semiconductor devices even under the atmosphere of a high temperature.
In the case where this Au--Au eutectic technique is used to connect a package substrate and semiconductor devices together, conventionally, a metal layer is formed on the surface of the Si substrate of the semiconductor devices which is mounted on the package substrate, and an Au layer is formed on the top surface of this metal layer to form Au--Au eutectic layer. The metal layer is a barrier metal to prevent diffusion between Au and Si, and is normally formed of Ti or the like.
When a package fabricated by mounting semiconductor devices on a package substrate by the Au--Au eutectic technique is exposed to a high temperature, another problem arises. With the package exposed to a temperature of, for example, 370.degree. C. or higher, diffusion between Au and Si cannot be prevented even when the conventional barrier metal of, for example, Ti is formed on a semiconductor device.
The mutual diffusion of Au and Si provides the same structure as the one where an Au--Si eutectic alloy layer is formed. The melting point of the Au--Si eutectic alloy layer is 370.degree. C., which is relatively low among those of eutectic alloys. When the mutual diffusion of Au and Si occurs at a high temperature of 370.degree. C. or higher, the Au--Si eutectic alloy layer is melted so that the portion near the barrier metal becomes susceptible to a high temperature while the Au--Au eutectic layer oriented junction shows an excellent heat resistance. In other words, when a package fabricated by mounting semiconductor devices on a package substrate by the Au--Au eutectic technique is exposed to a high temperature, misalignment occurs near the barrier metal.
A description will now be given of the case where a field discharge type electron source is mounted on a package substrate using the Au--Au eutectic technique. In using a field discharge type electron source for a CRT, after the field discharge type electron source as a semiconductor device is mounted on a package substrate, this package substrate is exposed to a high temperature of about 400 to 500.degree. C. in the step of sealing the resultant structure with glass as the CRT. In a later process of discharging air from the glass container (discharging step), the semiconductor device and the package substrate (package) are also exposed to a high temperature of about 400 to 550.degree. C. As a result, the junction between the semiconductor device and the package substrate is also exposed to a high temperature.
Although the semiconductor device and the package substrate are connected together by the Au--Au eutectic technique, therefore, misalignment of the semiconductor device on the package substrate occurs near the barrier metal of Ti and the like. When the field discharge type electron source is used for the CRT, the misalignment of the semiconductor device on the package substrate results in irregular colors or color deviation caused by misconvergence.
If the misalignment of a semiconductor device on a package substrate in any other package becomes greater, the distance between the bonding pad of the semiconductor device and the bonding portion of the package substrate becomes longer, thus making it difficult to connect the semiconductor device and the package substrate together.